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(COMP381)067ef1 - midterm-sol.pdf
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COMP 381 Design and Analysis of Computer Architectures
Fall Semester 2009
Midterm Examination
Date: 31 Oct. 2009 Time: 3:00 pm - 5:00 pm
Name:__SOLUTION_________ Student ID: ________________Email:____________________
Instructions
1. Please write your name, student ID and email address on this page.

2. Please answer all the questions within the space provided on the examination paper. You may use the back of the pages for your rough work.

3. This paper consists of 8 questions and 7 pages.

4. Please read each question very carefully and answer the questions carefully and clearly to the point. Make sure your answers are neatly written, legible and readable.

5. Show all the steps used in deriving your answer, wherever appropriate.




Question
Points
Score

1
10


2
10


3
10


4
10


5
15


6
15


7
15


8
15


Total
100






1. (10 points) Answer the following true/false questions by circling either T or F.

a) Word mis-alignment in memory can increase the number of memory reads and writes by the processor. T F

b) Increasing the pipeline depth of a microprocessor will always result in better performance. T F

c) In a load/store architecture, the only instructions that access memory are ALU operations. T F

d) Loop-level parallelism is a technique used to achieve better branch prediction. T F

e) Professional benchmarks typically use Geometric mean to compare the performance of different processors. T F

f) Using a scoreboard instructions are issued out of order by a processor. T F

g) RAW hazards can be eliminated through register renaming. T F

h) A pipeline that issues one instruction per cycle can have CPI < 1. T F

i) Memory indirect addressing mode requires one access to memory to fetch the operand. T F

j) A computer that stores 0xA987654321FED1BA in the following way is using little endian. T F















2. (10 points) Suppose a CPU supports both integer and floating point (FP) instructions. Integer instructions take one cycle to complete, while FP instructions take 5 cycles to complete. Suppose a program contains 40% of FP instructions.

a) Calculate the average CPI for the processor.



CPIoriginal = 40% x 5 + 60% x 1 = 2.6


b) Suppose now we speedup the FP operations three times.What will be the effective CPI in this case for the new processor?



CPIenhanced = 40% x 5/3 + 60% x 1 = 1.26666667


c) What is the effective speedup obtained for the new processor?



Speedup = 2.6 / 1.2666667 = 2.0526315789473684210526315789474


3. (10 points) A functional unit can be divided into k stages. The execution time for the i-th stage is ti for 0 . i . k-1. For the corresponding pipelined functional unit design, the delay introduced by each pipeline register (betwe