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COMP 381 L1 Quiz #1
35 minutes
Name: __________ Student No.: __________ Lecture Section: ___



In some questions, you may need to write MIPS instructions in assembly language. As examples, below are some instructions in assembly code:
Load a word from memory to r1: LW r1, 100(r2)
Store a the word in r3 to memory: SW r3, 100(r4)
Add r6 and r7 and assign the result to r5: ADD r5, r6, r7
Add r6 and an immediate, and assign the result to r5: ADD r5, r6, 200
Branch to address indicated by Label9 if r8 is zero: BEQZ r8, Label9


Q1. [15 Points] True, false, and why?
Determine whether the following statements are true or false, and briefly explain your point.

i.
Suppose two machines of A and B are using the same Instruction Set Architecture (ISA) and the same complier (i.e., they will have the same Instruction Count for a given program). A is running in 100MHz and B is running in 75MHz. Then A is always faster than B.




False because B may have a smaller CPI, e.g., Pipeline and Cache

ii.
If we run two programs, P1 and P2, on the same computer and measure their execution time, the program with a smaller CPI will always have a shorter execution time.




False because the program with a smaller CPI may have a higher IC.

iii.
The execution time of benchmark programs (e.g., SPEC CPU2006) is not solely decided by hardware. The compiler and compiler optimization flags also affect the programs execution speed.




True. (The compiler and compiler optimization flags also affect the programs execution speed.)

Q2. [20 Points] Pipeline hazards

This question assumes a basic 5-stage MIPS pipeline WITHOUT forwarding. The five stages are IF, ID, EX, MEM, WB.

i.
(10 points) What are the main courses of control hazards?




Control hazards are mainly caused by branches and other instructions that change PC.


ii.
(10 points) Give an example of RAW hazard using MIPS ALU or load/store instructions (e.g., ADD, SUB, LW, SW).




ADD r1, r2, r3
SUB r4, r1, r3




Q3. [15 Points] Pipeline performance

This question assumes single-issue pipelines -- at most one instruction enters the pipeline per clock cycle.

i.
(5 points) What is the best CPI we can get with the 5-stage pipeline if in an ideal situation?




1


ii.
(10 points) Suppose we have old implementation of the 5-stage basic MIPS pipeline. In the old implementation, each instruction spends 10ns in each of the five pipeline stages. Now we have hired a new engineer who is very good at circuit design. He tells us that he can improve the circuit in the five stages so that the time it takes for an instruction to complete its operation in the 5 stages becomes 3ns, 3ns, 5ns, 10ns, 5ns, respectively, as shown in the figure below.





Old pipeline



Proposed new pipeline

Can this proposed new pipeline enhance the performan