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(COMP381)quiz1_sol_comp381_by_PPSpider.pdf
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COMP 381 Quiz #1 (Answers)
Note: individual quiz sheets may vary in some details
Q1. [15 Points] True, false, and why?
Determine whether the following statements are true or false, and briefly explain your point.
i.
A 100MIPS computer is always faster than an 85MIPS computer (MIPS: Million Instructions Per Second)
False. Because the type of instructions are not specified.
ii.
If we run two programs, P1 and P2, on the same computer and measure their execution time, the resultant CPI should be identical for these two programs.
False. CPI depends on the program executed. Different programs have different instruction mix, and thus different CPI.
iii.
The execution time of benchmark programs (e.g., SPEC CPU2006) is not solely decided by hardware. The compiler and compiler optimization flags also affect the programs execution time.
True. The compiler and compiler optimization flags also affect the programs execution speed. They affect the number of instructions a program uses, the types of instructions it uses, and order these instructions are used.
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Q2. [20 Points] Pipeline hazards
This question assumes a basic 5-stage MIPS pipeline WITHOUT forwarding. The five stages are IF, ID, EX, MEM, WB.
i.
(10 points) What is the definition of structural hazards?
Structural hazards are caused by conflicts on hardware resources because the processor does not have sufficient resources to handle the combination of instructions in the pipeline.
ii.
(10 points) Give an example of RAW hazard using MIPS ALU or load/store instructions. Limit the number of instructions to 5 at maximum.
ADD r1, r2, r3
SUB r4, r1, r3
Instruction examples: In some questions, you need to read or write MIPS instructions in assembly language. Below are some examples of instructions in assembly code:
Load a word from memory to r1: LW r1, 100(r2)
Store a the word in r3 to memory: SW r3, 100(r4)
Add r6 and r7 and assign the result to r5: ADD r5, r6, r7
Add r6 and an immediate, and assign the result to r5: ADD r5, r6, 200
Branch to address indicated by Label9 if r8 is zero: BEQZ r8, Label9
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Q3. [15 Points] Pipeline performance
This question assumes single-issue pipelines -- at most one instruction enters the pipeline per clock cycle.
i.
(5 points) What is the best CPI we can get with the 5-stage pipeline if in an ideal situation?
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ii.
(10 points) Suppose we have an old implementation of the 5-stage basic MIPS pipeline. In the old implementation, each instruction spends 10ns in each of the five pipeline stages. Now we have hired a new engineer who is very good at circuit design. He tells us that he can improve the circuit in the five stages so that the time it takes for an instruction to complete its operation in the 5 stages becomes 3ns, 3ns, 5ns,