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(EESM501)[2009](f)final~1833^_22924.pdf
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HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY
Department of Electronic and Computer Engineering
EESM 501 - CMOS VLSI Design
Fall 2009
December 10, 2009 Final Exam Duration: 150 minutes
Write clearly. You can write to the back of the papers. Do not hesitate to ask for additional blank papers if you need.
You cannot leave the exam room within the last 10 minutes of the exam.
(a) (5pt) Draw the circuit schematic. Clearly show all the inputs on the schematic to match the layout. Each correctly shown transistor and input: 0.5pt
(b) (2pt) Determine the logic function of this circuit.
F = (E + D) . (A + B + C)
2pt
(c) (8pt) Consider the following input vector transition: ABCDE = 11111 -> 00011
C is known to arrive (1 -> 0 transition) earlier as compared to A. B is known to arrive (1 -> 0 transition)
earlier as compared to C.
Would you recommend a pin reassignment to enhance the output transition speed as compared to the original pin assignments shown in the layout?
If your answer is yes, redraw the circuit with the new pin assignments.
If your answer is no, explain why the current pin assignments (as shown in the layout) are optimum for achieving the maximum output transition speed with these inputs.
2pt
Yes, a pin reassignment is recommended to enhance the speed. The earlier arriving signals should be applied to the transistors closer to the power supply. With the following pin assignments, C3 will be charged to VDD when B arrives. After some delay C will arrive. C2 will be charged to VDD. When finally A arrives, the pullup path (through P1, P2, and P3) needs to charge only CL since C2 and C3 are already fully charged to VDD. Output low-to-high transition would therefore be faster with the pin
Q2 (19pt) Consider the following clocked circuit.
Stage1: TPLH = H1, TPHL = L1 Stage2: TPLH = H2, TPHL = L2 Stage3: TPLH = H3, TPHL = L3 Stage4: TPLH = H4, TPHL = L4
L1 < L2 < L3 = L4 H2 = H3 = H4 < H1
(a) (12pt) Fill in the following table for each phase of the clock signal (clk = 0V and clk = VDD) assuming Data = 0V. Determine whether stage1, stage2, and stage3 are transparent or opaque. Fill in the voltages of node1, node2, and output shortly before each clock edge for Data = 0V.
t0 t1
t0 t1
CLK = VDD
CLK = 0V
CLK = 0V
CLK = VDD
(shortly before the positive
(shortly before the negative
clock edge)
clock edge)
Stage1
Transparent
Opaque
Stage2
Opaque
Transparent
Stage3
Opaque
Transparent
Node1
VDD
VDD
Node2
VDD
0
Output
(previous state)
0
1pt
Each correct entry in the Table:
(b) (7pt) Determine the setup time, the hold time, and the propagation delay of this register assuming the valid data is 0. Use the delay information provided with the figure.
2pt
Setup time = H1
2pt
Hold time = L2
3pt
Propagation delay (tpCQ) = L2 + H3 + L4
Hold
time
Setup
time
CLK = 0V
DATA
Q3 (20pt) Consider the following circuit. The