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(EESM501)[2009](f)quiz~1833^_44799.pdf
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HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY
Department of Electronic and Computer Engineering
EESM 501 - CMOS VLSI Design
Fall 2009
November 19, 2009 Quiz 2 Duration: 30 minutes
STUDENT NUMBER: FAMILY NAME (SURNAME): FIRST NAME:
SOLUTION
TURN OFF YOUR PHONE
Write your student number, family name, and first name (no acronyms).
Copy sheets and books are NOT permitted.
No electronic equipments. NO CALCULATORS.
Write clearly. You can write to the back of the papers. Do not hesitate to ask for additional blank papers if you need.
You cannot leave the exam room during the quiz.
Q (14pt) Consider the following layout. All the transistors have minimum channel length. All the contacts are 4 * 4. The metal-wire width is 3. VDD = 2.5V.
(a)
(0.6pt) Identify the three components pointed on the figure.
(b)
(1.4pt) Draw the schematic of the circuit. Show all the capacitors that affect the delay of the first gate. Clearly label all of the transistors and capacitors on the schematic.
Vdd 0.2pt Vdd Vdd
Vdd Cg_P2
Each correctly shown capacitor = 0.2pt
(c) (7.2pt) Fill the following table with the source junction area, drain junction area, source junction perimeter, and drain junction perimeter of the transistors of the first gate. Give the values in terms of . Identify each transistor clearly in the table. Use the transistors labels from part b.
Transistor
Source
junction
area
Drain
junction
area
Source
junction
perimeter
Drain
junction
perimeter
T1
T2
Transistor
Source
junction
area
Drain
junction
area
Source
junction
perimeter
Drain
junction
perimeter
T1 (N1)
5*6
5*6
5+6+5
5+6+5
T2 (P1)
5*12
5*12
5+12+5
5+12+5
Each correct entry = 0.9pt
d) (4.8pt) Assume the voltage across a p-n junction transitions from V1 to V2. The effective (equivalent) junction capacitance coefficient is
. m
b 1.m 1.m
K = [(.V ) . (.V )]
eq b 1 b 2
(V1 .V2 )(1. m)
where m is the junction grading coefficient and b is the built-in junction potential. V1 and V2 are the initial and final voltages across the junction, respectively. V1 and V2 are negative for reverse bias and positive for forward bias. VDD = 2.5 V.
Determine the initial and final junction voltages V1 and V2 experienced by the transistors of the first gate for the output-low-to high and output high-to-low transitions. While determining the initial and final junction voltages, consider only the junctions that affect the propagation delays.
Output low to high transition:
N1-drain: V1 = 0V and V2 = -1.25V
Each correct voltage = 0.6pt
P1-drain: V1 = -2.5V and V2 = -1.25V
Output high to low transition:
N1-drain: V1 = -2.5V and V2 = -1.25V
Each correct voltage = 0.6pt
P1-drain: V1 = 0V and V2 = -1.25V