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(ELEC101)[2011](s)quiz~kchungaa^_55321.pdf
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IDNo. _ Chinese Name: _ Lecture__:;!.L~1_~/ L~2=-_
Number Max Score Score Number Max Score Score
1 1 7 2
2 2 8 5
3 2 9 5
4 1 10 4
5 1 11 5
6 2 Total 30

Useful infonnation: 109 B G 10-3 Bm

10-12 Bp This is a CLOSED book and CLOSED notes examination. Part A:
1. Find Vo in Fig. P-l. 1 mark

Fig. P-l
--------~-_.._----7
[Vl7:' '-L-f'V
~_~......__.._... ..--J.
HKUST 2011 Spring Quiz 1 -1 KilKwok
2. Find the power absorbed or delivered by the voltage source and the 2 marks current source in Fig. P-2 (absorbed is +ve, delivered is -ve).
3V
Lvo l-t~ ~~=~-l

Fig. P-2
Po w~r --I-(3)( ~) -
-t (; w ( Q\-b 50 r hed )
iC"" (~ -;~1
Po We,. ;:. -(s)( v) --(; Lv C del;ve r~)
3. Convert 2810 into an 8-bit binary number. 2 marks You need to show your steps to get points
2
' ~.
0
lif
2 E
--0
2. 12
----_...... I
1_12
J
---I

ELEC 101 Quiz 1 March 22 7pm-8:15pm

4. Write down the logic function Z in Fig. P-4 as a function ofA, and B. 1 mark
No need to simplify the answer.
5. Compute the equivalent resistance ofthe resistor network in Fig. P-5. 1 mark



Ref; =-I"R /IC I~ f-
!R1' ~-t ~ ]
ELEC 101 Quiz 1 March 22 7pm-8:15pm
6. Compute and draw Thevenin's equivalent circuit of the circuit in 2 marks
Fig. P-6. (Compute Voc and Rt ofthe circuit to the left of a-b.)
a



"?,J b
Fig. P-6
J:=tr~i4]

[Vo~
v: ~~ (I TV)) ( J.-J...) -V
2.
rV~ -.=-0
V-th-=->.;
1--~"""----'70 "\
v~~ 2 V

t---_---:_~
h
ELEC 101 Quiz 1 March 22 7pm-8:15pm
7. Use nodal analysis or loop analysis to solve for Va in Fig. P-7. 2 marks
sv
21<.0


I/~ -0 J,~ -0

-------.----.---.--J

1
\/fJ'-::. 2-V(----_._..-._--
Part B:
8. Binary numbers 5 marks
(8a) ConvertA =27\0toan8-bit2'scomplementnumber. 1mark Show your steps.
27/0 =-0 00 I I 0 JI
(8b) Convert B =-3810 to an 8-bit 2's complement number. 2 marks Show your steps.
II 0 110/0
-3<i/o 'I(ollot..? I -
..
(8c) Perfonn addition ofC =A +B. What is C in 2's complement? 1 mark Show your steps.
DOO 'f Or(
f I/ull 010

! If {O 101


(8d) Convert C back into base 10. Show your. steps. 1mark
9. Digital Logic 5 marks

Fig. P-9
(9a) Write the output E in tenns ofAND and OR gates. 1 mark You may assume A, C and their complements are available as inputs.
-
E A C -r AC

(9b) Use truth table to show that DeMorgan's law: X Y =X +Y is true. 1 mark
?< 'f
o 0
() l
I 0
( I

. /.~
f--y,--~~--M~'--+--\ +-'f-t' y 1

I
J () 0 I
o ()
I
,
o

ELEC 101

March 22 7pm-8:1Spm
(9c) Using the results Qf(9a),' ik~;P~9,such that only 3 marks NAND gates are used..'tj' complements are available"

ELEC 101 Quiz 1 March 22 7pm-8:15pm
10. Circuit Analysis 4 marks
With reference to the circuit shown in Fig. p-lO, use appropriate
analysis method (voltage/current division, nodaVloop analysis) to
solve for