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(ELEC151)2006_s_midterm1_elec151.pdf
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06-1. 2006 Elec151 Midterm Exam #1, p2/8 Boolean Expressions and K-map (20%) Given a Boolean function F(A,B,C,D) = m(1,2,3,11,12,14) + d(0, 7, 15) a). Simplify this Boolean function in sum of minterms. (5%) b). Simplify this Boolean function in product of maxterms. (10%) c). In CMOS technology, what is the minimum number of transistors required to implement this function in two-level design. (5%) 06-2. 2006 Elec151 Midterm Exam #1, p3/8 Multilevel Logic Gates and Analysis (20%)) Obtain the most simplified Boolean expressions for output F and G in 2-level sum of minterms. (20%)

06-3. 2006 Elec151 Midterm Exam #1, p4/8 XOR/XNOR functions (20%) Design a 4-input odd function F(A,B,C,D) by a) Only NAND gates (10%) (Conventional design procedure in 2-level sum-of-product form by k-map, just write down the most simplified Boolean expressions) b) Only XOR gates and/or XNOR gates (10%) (Through physical meaning, please draw the schematics with only XOR and/or XNOR gates) 06-4 2006 Elec151 Midterm Exam #1, p5/8 Implementation Methods (20%) Given a 4-input Boolean function F(A,B,C,D) = m(4,5,6,8,9,10,13) + d(0, 7, 15) a). Implement the function using an 8:1 multiplexer and an inverter. (5%) b). Implement the function using a 4:16 decoder and an OR gate. (5%) c). Implement the function using a 4:1 multiplexer and minimal primitive gates. (10%)

(This page is intentionally left blank for answer or practice) 06-5 Design with TTL ICs (20%) 74LS83 is a 4-bit binary adder that we used in the laboratory. 74LS85 is a 4-bit magnitude comparator that we briefly introduced in the lecture. Their logic blocks and truth table are shown below. Use these logic blocks for the following questions.
74LS83 A1
74LS85
(a) Design and draw an 8-bit binary adder that adds A (A7A6A5A4A3A2A1A0) and B (B7B6B5B4B3B2B1B0) for C (C8C7C6C5C4C3C2C1C0) with 2 74LS83. (5%) (That is to do A + B = C) (b) Design and draw an 8-bit magnitude comparator that compares A (A7A6A5A4A3A2A1A0) and B (B7B6B5B4B3B2B1B0) with 2 74LS85 for three outputs which are F1 for A>B, F2 for A=B and F3 for A<B. (5%) (That is to do F1 =1 when A>B, F2=1 when A=B and F3=1 when A<B) (c) Design and draw a 4-bit by 3-bit binary multiplier that multiplies A (A2A1A0) and B (B3B2B1B0) for C (C6C5C4C3C2C1C0) with 74LS83 and 2-input AND gates from 74LS08. How many TTL ICs are required for this multiplier? (10%) (That is to do A x B = C) (Note that all the inputs have to be connected in the above three designs.)
2006 Elec151 Midterm Exam #1, p6/8 2006 Elec151 Midterm Exam #1, p7/8

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2006 Elec151 Midterm Exam #1, p8/8