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(elec151)[2009](s)final~2286^_10016.pdf
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Name:__________________________ Student I.D. Number: ______________________
ELEC 151: Digital Circuits and Systems
(Fall 2009)
Final Examination
Date: 10/12/2009 (Thursday)
Time: 4:30 -7:30 p.m.
1.
There are five questions in this examination. Answer all questions in this question booklet.
2.
Write down your name and student ID number in this page and put your student ID# at the upper left corner of each page in this booklet.
3.
Answer all the questions in the space provided.
4.
Some sub-questions are marked with an (*). It means that this sub-question may take more time to finish. You can plan your time accordingly.
Question Number Total Marks Score
1 10
2 43
3 20
4 20
5 20
Total 113
1. (10 marks) True and False Questions C Important notes: Each sub-question carries 1 mark. If you answer it correctly, you have 1 mark. If your answer is not correct, you get -0.5 mark, i.e. you will be deducted 0.5 mark. No mark will be given or deducted if you do not give any answer.
a. (1 mark) The following circuit is a memory element.
Answer:______________________
b. (1 mark) For a finite state machine (FSM), different state assignments will result in
different state transition diagrams.
Answer:_____________________
c. (1 mark) Company A wants to design a chip for the 3G phone market and it is expected that they can sell 10 million of the chip per year. They should implement their chip using FPGA.
Answer:_____________________
d. (1 mark) The following VHDL code describes a register that has active high synchronous clear.
Answer:_____________________
e. (1 mark) Ring counter can be implemented by just cascading flip-flops without additional logic. If we use Johnson counter to implement a ring counter, it can also be implemented by just cascading flip-flops without additional logic.
Answer:_____________________
f. (1 mark) The following state transition diagram describes a Moore machine.
Answer:_____________________
g. (1 mark) For a N-bit address decoder, there are log2N output.
Answer:______________________
h. (1 mark) For a rising edge-triggered flip-flop, if the input changes within the setup time before the rising clock edge, the data stored in the flip-flip after the clock edge may not be correct.
Answer:______________________
i. (1 mark) For a FMS that has N states, we cannot use more than .log2 N. number of flip-flops to implement the states.
Answer: _____________________
j. (1 mark) The following is a rising-edge triggered D-flip flop.
Answer:______________________
2) Short question (43 marks)
a) (3 marks) A finite state machine (F) has 6 states. If we use 3 D-Flip Flop to implement the states, how many different state assignments do we have? b) (5 marks) Let A be positive level-sensitive D-latch and B be a rising-edge