=========================preview======================
(ELEC202)pass_final.pdf
Back to ELEC202 Login to download
======================================================
THE HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY
DEPARTMENT OF ELECTRICAL AND ELECTRONIC ENGINEERING
Elec 202 Philip Mok
ELECTRONIC CIRCUITS II
Fall 2002 Room 2440
FINAL EXAM
(16 December 2002 4:30 pm - 7:30 pm)
Name: ___________________________ Student No.: _________________________
Seat No.: ___________________________ Signature: _________________________
VBE .VT
Given: For BJT in active region, IC = ISe 1W 2
For MOS in pinch-off region, = 2 --
C..----L -(VGS C )
ID ox.. Vt
W
..
For MOS in triode region, ID = C-----
ox
..
L
Question 1: (20 marks)
12
( C Vt)C --
VDS
VGS VDS
2
Consider the amplifier below, all transistors have Vt = 1 V, nCox = 10 A/V2 and = 0.2 V.1.
(a)
Find the drain current and the DC voltage at each terminal of each transistor, M1 and M2. [4]
(b)
Find the input and output resistance Ri, Ro and the voltage gain vo/vi of the amplifier. [12]
(c)
Find the minimum transistor size ratio (W/L)2 of transistor M2 such that the amplifier operates properly in its pinch-off regions. [4]
VDD = 10 V
vo
600 k. R1
100 k.
200 k.
Rs
W 20
..
M1 -----= ---------
..
L2
1
10 k.
vi
200 k. R3
Question 2: (15 marks)
The current mirror below is called a peaking current source because the output current IO has a peak value as the input current II is changed. Assume the transistors are matched with very large and VA, Q2 operates in forward active region and VT = 26 mV.
(a)
Derive an equation for IO as a function of II. [5]
(b)
Find the condition of II when the peaking of the output current occurs. [5]
(c)
Find the value of the peak output current when R = 100 .. [5]
II
IO
R
Q2
Question 3: (20 marks)
The three-input pseudo-NMOS complex gate below has three identical NMOS transistors and a PMOS transistor with Vtn = 1 V, Vtp = .1 V and nCox = 2pCox.
(a)
What is the logic function of the complex gate? [2]
(b)
Find the voltage at X when A is low, B and C are high, and the output Y equals to 1 V. [7]
(c)
Find the transistor ratio (W/L)p of the PMOS transistor such that the complex gate satisfies the condition stated in part (b). [7]
(d)
Assume a constant current charging and discharging, estimate the ratio of the worst case propagation delay tpHL(worst) to the best case propagation delay tpHL(best). [4]
VDD = 5 V
W
..
..
Mp Lp
Y
CL
W 10
..
B
Mn2 .. =
L2
n
W 10
..
X
A
=
Mn1 ..
L2
n
W 10
..
C
Mn3 -----= ---------
..
L2
n
Question 4: (25 marks)
The single-ended output differential amplifier below is biased with a 1-mA current source. All transistors are matched with = 100, VA = 100 V and VT = 26 mV.
(a)
Find the DC biasing currents of Q1 and Q3 and the DC voltage at vo with zero input voltage. Assume = in this part of calculation. [4]
(b)
When vi is driven by a single voltage source