=========================preview======================
(elec254)[2007](s)mid~PPSpider^_10311.pdf
Back to ELEC254 Login to download
======================================================
HONG KONG UNIVERSITY OF SCIENCE OF TECHNOLOGY
DEPARTMENT OF ELECTRONIC & COMPUTER ENGINEERING
ELEC 254 Microprocessor Experiments
Midterm (13:15 C 14:45 21 April 2007)
Prof. Kam-Tim WOO
I declare that the answers submitted for this examination are my own work. I understand that sanctions will be imposed, if I am found to have violated the Universitys regulations governing academic integrity.
Name : Answer
Student ID :
Student's Signature :
Remarks :
1. This is an open book examination.
2. Answer all questions in the space provided.
3. Show all your procedures clearly. No marks will be given for unjustified answers.
Questions
Maximum Marks
Marks
1
10
2
8
3
12
4
6
5
12
6
12
7
15
8
25
Total
100
Question 1 (10 marks)
Write an instruction sequence to initialize the serial port to operate a 9-bit bi-directional UART at 1200 baud. Assume that the 8051 is operating from an 11.0592MHz crystal and Timer 1 is employed.
Answers:
MOV PCON,#0xxxxxxxB
MOV SCON,#1101xxxxB
MOV TMOD,#20H
MOV TH1,#0E8H
MOV TL1,#0E8H
SETB TR1
Question 2 (8 marks)
What is the effect of the following instruction?
MOV TMOD, #00101101B
Answers:
It will set Timer 0 to mode 1 as a counter, and since Gate bit = 1, Counter will get the clock from T0 pin of the 8051 and only count when /INT0 = 1 and TR0 = 1.
It will set Timer 1 to mode 2 as a timer with Gate bit = 0. i.e. Timer 1 will run when TR1 = 1.
Question 3 (12 marks)
A SRAM memory architecture is implemented in the Figure 1.
Figure 1
(a) (4 marks) What is the capacity of this architecture?
Answers:
A0 C A23 = 24 bit address = 16 M Bytes
i.e. 000000H to FFFFFFH
(b) (4 marks) How many SRAMs are needed in this memory architecture?
Answers:
Each SRAM got 20 bits address = 220 bytes = 1 M Bytes
Total # of SRAM needed = 224-20 = 24 = 16 SRAM
(c) (4 marks) Which SRAM(s) is / are accessed if the memory is ranged from 0F2802H to 1F2604H?
Answers:
SRAM 0: 1st SRAM address is from = 000000H C 0FFFFFH
SRAM 1: 2nd SRAM address is from = 100000H C 1FFFFFH
A0 C A23
A0C A19
A0C A19
A0C A19
A20 C A23
A0 C A19
A0 C A19
A0 C A19
Question 4 (6 marks)
Why would DMA be useless if the computer did not have interrupt capability? (Please answer in less than 80 words)
Answers
Since DMA controller will handle all the memory read/write processes and will inform the computer by interrupt, so, if the computer does not have interrupt capability, the DMA controller will not be able to tell the computer that it finished the transfer
Question 5 (12 marks)
The con