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(ELEC301)[2006](sum)midterm~818^_10314.pdf
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ELEC301, Midterm exam paper, Summer 2006, 10th July, 2006
Question 1: Short answer questions (8marks)
1.1 For Fig1.1, assume Vin = 5V and V2 = 0.2V, the operation mode of transistor G1 is ..........
Vout is .............(2marks)

5V 5V
a) saturation mode ; 5V
b) linear mode ; 5V


G1
c) cutoff; 5V
d) saturation mode ; 4.5V


Vout
e) linear mode; 4.5V
V2
Vin

Vtn = 0.5V
f) cutoff ; 4.5V

Vtp = -0.5V

Fig 1.1


1.2 For the circuit shown in Fig 1.2, find the final value of the voltage Vo. Assume Vtn=|Vtp|=0.6V (ignore body effect). (2marks)

Fig 1.2

1.3 In a N-substrate, Pwell based process, is it possible to avoid body effect in both the NMOS and PMOS transistors? Explain why or why not. (2marks)
Body effect is avoided if Vbs=0.
In a N-substrate Pwell process, this can only happen for a NMOS transistor because we can design the
layout such that each NMOS will have its own well, which will be then tied to GND and hence Vbs is
null.

This however cannot be done for PMOS
because in PMOS device the substrate is the same for all transistors.

1.4 Explain why and how the polarization of the both substrates is performed in a N-substrate, Pwell CMOS process. (2marks)
In a CMOS process, every p-n junction constitutes a diode and these need to be reversed biased otherwise current will flow between the substrates and the different nodes of the transistors. To reverse bias the diode, N substrate should be connected to VDD and Pwell should be connected to GND.
- 2 C

ELEC301, Midterm exam paper, Summer 2006, 10th July, 2006
Question 2: (6marks)

2.1 The sequence of carrying out the Source/Drain implantation of PMOS transistors is..(2marks) a) after N wells built. b) before poly gates built.
c) after poly gates built d) before active regions formed.
e) after active regions formed.

2.2 For the 3D silicon structure represented in Fig 2.1, the layers found across the dotted line A is/are: (2marks)
a) Metal1 layer, Pimp layer.
b) Metal1 layer, Nimp layer and Contact layer
c) Metal1 layer, Pimp layer and Oxide layer.



Figure 2.1

2.3. Across the layers found across the dotted line B is/are: (2marks) a) Poly layer. b) Poly layer and Oxide layer. c) Poly layer and Nimp layer.
d) Poly layer, Oxide layer and Nimp layer. e) None of above
- 3 C

ELEC301, Midterm exam paper, Summer 2006, 10th July, 2006 Question 3: (14marks)
3.1 For Figure 3.1, the drain of the PMOS transistor B is. and the drain of the NMOS transistor C is. (3marks)
a) B: y , C: o
b) B: x , C: p c) B: w , C: p
d) B: x , C: m

3.2 For Figure 3.1, the logical function at node Out is ...... (3marks)
a) Out = (B + C) . A
b) Out = (A + B) . C
c) Out = (A + C) . B


d) none of above Fig.3.1


3.3 For the layout of figure 3.2b a) Point out in the schematic (fig. 3.2a) both nodes x and y. b) Point out in the schematic (fig. 3.2a) all the gates i.e: A, B, C, D, E and