(ELEC303)midsol_00.pdf

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4. Routing (10%) 5. Traffic Light Controller (20%)

Is it possible to connect pin 2 of L00 to pin 5 of L44, pin 1 of L04 to pin 6 of L42, The whole traffic light controller logic can be implemented by a FPGA.

pin 8 of L02 to pin 8 of L42 and pin 4 of L22 to pin 3 of L24? If yes, please rount the a). Estimate how many XC3000 CLBs are required? (10%)

connections. If no, please mark the connection or switch block, which does not have b). Estimate the equivalent gate count for this traffic light controller. (10%)

enough flexibility. Note that the traffic light controller has one FSM and three sub-systems.

Reset Clk short time/ long time

L04 L24 L44 TS TL counter ST

Reset C (async) Clk Car Sensor C (sync) Next State Output Logic controller fsm 2 2 2 Encoded Light Signals Light Decoders F 3 3 H

2 State

Register

L02 L22 L42 FSM: 4.5 CLBs according to page 3-31 of lecture notes P1 has 4 3-NAND and 1 4-NAND = 4 x 1.4 + 2 = 8

P0 has 3 3-NAND and 1 2-NAND = 3 x 1.5 + 1 = 5.5

ST has 4 3-NAND and 1 4-NAND = 4 x 1.5 + 2 = 8

H1 has 3 3-NAND and 1 2-NAND = 3 x 1.5 + 1 = 5.5

H0 has 2 3-NAND and 1 2-NAND = 2 x 1.5 + 1 = 4

F1 has 0 gate

F0 has 2 3-NAND and 1 2-NAND = 2 x 1.5 + 1 = 4

In total = 35 gates

Light Decoder: 6 functions of 2 inputs ( for example FG = F0 F1, FY = F0 F1, ..)

L00 L20 L40 2 functions per CLB . 3 CLBs Each function requires about 1.5 gates . 1.5 x 6 = 9 gates

Car Detector: 0.5 CLB, 2 + 4 = 6 gates

Timer: 2 functions and 4 FFS for the 4-bit counter. . 2 CLBs

2 x 2 + 4 x 4 (if it is a simple ring counter) = 20 gates

a). 4.5 + 3 + 0.5 + 2 = 10 CLBs

b). 35 + 9 + 6 + 20 = 70 gates

Elec303, 2000 midterm solution , pp.5/6 Elec303, 2000 midterm solution , pp.6/6