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(ELEC303)midsol_02.pdf
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2002 ELEC 303 Midterm Examination (4 questions)
0.
Write down your NAME: Model Answers
and STUDENT NUMBER:
Answer only on two sides of the question papers.
1.
Mapping, Placement and Routing (20%)
A state machine has the following state equations
Q1+ = SQ1 + Q2
Q2+ = S + TQ2
Z = SQ1 + Q2 + S + TQ2 = (S + SQ1) + (Q2 + TQ2 )= S + Q2 WhereQ1 and Q2 are state registers; S and T are inputs; and Z is output. Q1 has been placed and mapped into a logic block below.
Complete the implementation of this state machine by writing 0 or 1 into the SRAM cells. Please also highlight the routing wires. (Hint: Firstly re-express each function in truth table and write output values into the look up tables, then complete routing between logic blocks.)
Q1 Q2 S Q1+Z
0 0 0 0T
0 0 1 0S
0 1 0 1
00
0 1 1 1
00
1 0 0 0
111
0
1 0 1 1
11
1 1 0 1
1
0 Q1
1 0
1
1 1 1 1
1
1 Z1 11
Q2 T S Q2+
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
0
1 0 0 0
1
1 0 1 1
0
1 1 0 10
1
1 1 1 1
0 Q2
1
1
S Q2 - Z
1
0 0 X 0
1 0 0 X 0 0 1 X 1 0 1 X 1 1 0 X 1 1 0 X 1 1 1 X 1 1 1 X 1 Logic optimization is part of design process before place and route!
2. Technology Mapping (20%) Map the following circuit to 3-input LUTs with the Chortle-crf technology mapper. Keep track of all the important lists. Draw the final circuit.
a b c d e f g h i j k lmno p
A D G L
A
D G I
x y
X G1 L1
z Y
All leaf nodes are assigned a buffering LUT
Z
. circuit (a, b , c, d, e, f, . . . . . . ,n, o, p)
YZ
At node A, LUT a, b and c are merged to LUT A
. circuit (A, d, e, f, . . . . . . , n, o, p)
At node D, LUT d, e and f are merged to LUT D
. circuit (A, D, g, h, i, . . . . . . , n, o, p)
At node G, LUT g, h, i, j and k are packed to (g, h, i,) and (j, k) by the FFD
The DecomposeNode directs the output of (g, h, i) to (j, k)
And create a new LUT G1, which has 3 inputs G, j and k
. circuit (A, D, G, G1, . . . . . , n, o, p)
At node L, LUT l, m, n, o and p are packed to (l, m, n) and (o, p)
The DecomposeNode directs the output of (l, m, n) to (o, p)
And create a new LUT L1, which has 3 inputs L, o and p
. circuit (A, D, G, G1, L, L1)
At node x, its faninLUT A and D are sorted to (A[3], D[3])
Both faninLUT A and D remain the same and their outputs are pointed to
A new LUT X, which has 2 inputs A and D
. circuit (A, D, X, G, G1, L, L1)
At node y, its faninLUT G1 and G1 are packed to (G1[3], L1[3]) Both faninLUT G1 and L1 remain the same and their outputs are pointed to A new LUT Y, which has 2 inputs G1 and L1
. circuit (A, D, X, G, G1, L, L1, Y)
At node z, its fanin LUT X and Y are sorted to (X[2], Y[2])
LUT X remains the same and its output is pointed to
A new LUT YZ
. circuit (A, D, X, G, G1, L, L1, YZ)
8 LUTs are re