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(elec303)[2006](mid)sol~PPSpider^_10319.pdf
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2006 ELEC 303 Final/Midterm Examination (5 questions and 8 pages)
0. Write down your NAME: and STUDENT NUMBER:
Answer only on two sides of the question papers.
SPARTAN-II AND LABS (20%)
a) XC2S15-TG144-6 was used in the laboratory. What is the total number of slices in this device? How many 4-input look-up tables, flip-flops and input/output blocks are available in this device? (6%)
b) The Spartan-II device has a delayed lock loop (DLL) to generate and synchronize clocks. For an input clock of 50MHz, how many different clocks that this DLL can generate? (2%)
c) There are many possible ways to use block RAM in Spartan-II devices. How many block RAMs are available in XC2S15-TG144-6? If we need to store 2k x 16 bits information, how many block RAMs do we need and how do we configure these block RAMs? (6%)
d) The logic cell or look-up table in the Spartan-II device can be used as a 16-bit shift register shown below. Please design a 24-bit shift register with these 16-bit shift registers. How many slices are required in order to design an 80-bit shift register? (6%)

a) There are 92 CLBs, 92 x 2 = 192 slices, 192 x 2 = 384 4-input look-up tables and 86 input/out blocks. There are 384 flip-flops in CLB and another 86x3=258 flip-flops in IOB, so the total number of flip-flops is 384 + 258 = 642.

b) 6 different clocks.
c) 4 block RAM. Configure block RAM to 256 x 16 bits by RAMB4_S16 ( or 2k x 2 bits by RAMB4_S2) and we need 8 block RAMs.

5 SRLC16 are required for the 80-bit shift register. Each slice has 2 SRLC16, so 3 slices are required.
2. ASIC Development Cost (20%) It is known that the gate density of the TSMC 0.25 micron logic process (CL025) is 50k gates/mm2. The width and height are of the IO pads are 90m and 300m, respectively. Use standard price attached below for the following questions. a) The chip area includes bonding pad area and circuit area. The bonding pad area is on the perimeter and encloses the circuit area. What is the circuit area enclosed by 80 IO pads? What is the maximum gate count that can be implemented in this circuit area with CL025 process? (6%) b) What is the cost of producing 40 chips of this circuit with 84-lead LCC package and CL025 process? (4%) c) A designer has tried to transfer this design from CL025 process to CL018 process and used same kinds of IO pads, but has reduce the number of IO pads from 80 to
68. What is the cost of producing 30 chips of this design with 68-lead LCC package and CL018 process? (6%)
d) After the 90nm technology, what will be the next two advanced technologies in terms of feature size? What will be their gate density (# of gates per mm2)? (4%)

a) These 80 IO pads would divided to 20 on 4 sides, so the circuit area enclosed by these 80 IO pads would be in a square 20x90um long, or 3.24mm2 . The maximum gate count of the circuit would be 50k x 3.24 = 162k gates.
b) The total chip area includes bonding pad area and circuit area. The c