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(elec303)[2008](mid)sol~PPSpider^_10320.pdf
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2008 ELEC 303 Midterm Examination (5 questions and 8 pages)
0.
Write down your NAME: Modal Solution and STUDENT NUMBER:

Answer only on two sides of the question papers.

1.
FPGA fundamentals (20%) There are 4 partitions in the circuit and each partition is placed to a logic block in the FPGA as shown below. a). What is the placement? (4%)


(Or which block is assigned to partition P1, P2, P3 and P4, respectively.) b) Mark on the figure the node D, which might consist of quite a few segments. How many wire segment has it occupied? (4%) c). What is the critical path from which input (A, B or C) to which output (F or G)? And how many programmable switch elements has it passed through? (4%) d). Mark on the figure one connection block and one switch block if there are such blocks. What are the flexibility of the marked blocks, respectively? (8%)

a) P1 B1 P2 B4 P3 B7 P4 B10
b) 9 wire segments as shown on the figure
c) From B to F. It goes through 12 switch elements.
d) The SW and Connection blocks are shown on the figure
The flexibility of the SW
block is 3, and the flexibility of
the connection block is 3, too.
Elec303, 2008 Midterm Exam. Solution, pp.1/6
2. Mapping, Placement and Routing (20%)
A state machine has the following state equations
Q1+ = SQ1 + Q2

Q2+ = ST + TQ2
Z = SQ1 + STQ2
Where Q1 and Q2 are state registers; S and T are inputs; and Z is output. Q1 has been
placed and mapped into a logic block below. Complete the implementation of this state
machine by writing 0 or 1 into the SRAM cells. Please also highlight the routing wires.
Q1 Q2 S Q1+ Q2 T S Q2+ Q2 T S Z1 Z1 Q1 S Z
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0
0 1 0 1 0 1 0 0 0 1 0 0 0 1 0 0
0 1 1 1 0 1 1 1 0 1 1 0 0 1 1 1
1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 1
1 0 1 1 1 0 1 0 1 0 1 0 1 0 1 1
1 1 0 1 1 1 0 1 1 1 0 0 1 1 0 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Z
T
S

Q1 0 Z1 0
0 0
0 1 1 0
Q2 1 0 1 Q1 1 Q1 1 1 1 0
S 1 S 1 Z
1 1
Q2 0 Q2 0
0 0
0 0 1 0
T 1 0 0 Q2 1 T 0 0 0 0
S 1 1 S 0 1 Z1

SPARTAN AND SPARTAN-II (20%)
a) XC2S15-TQ144-6 used in the laboratory does not have enough capacity, so a XC2S200-PQ208-6 is used to implement a logic design. How many 4-input look-up tables and input/output blocks are available in this XC2S200-PQ208-6 device? How many SRAM cells are in this device? (6%)
b) List three differences between a 16x2 single-port RAM and a 16x1 dual-port RAM in Spartan-II. (3%)
c) Which Spartan FPGA has the most comparable performance with XC2S15-TQ144-6 and why? (5%)
d) The logic cell or look-up table in the Spartan-II device can be used as a 16-bit shift register as shown below. Please design a 33-bit shift register with as smaller number of CLB as possible. How many slices are required? (6%)

a) There are 1176 CLBs, 1176 x 2 = 2352 slices, 2352 x 2 = 4704 4-input look-up tables. (#6-9) The