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(ELEC504)284e62 - ELEC504_MidTerm_Solution.pdf
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ELEC 504 Oct. 30, 2009
Fall 2009 George Yuan

ELEC504 Mid-term Exam

Equations:
1) MOS channel thermal current noise density

22
diDS / df . 4kT gm
3

2) Resistor thermal noise density
diR 2/ df . 4 RkT
dvR 2/ df . 4kTR

3) Common-gate transistor input and output resistance
grR

mds S
RLm,

grds gr, ds
m


RS
rds
. RL
1. gr

mds

4) Gain-boosted cascode output resistance
Vdd
.gr ..gr . r
m3 ds 3 m2 ds2 ds1
g ,r

m2 ds 2
g ,r
m3

gr, ds
m11



1. (25pts) Sample and hold (S/H) operation can be performed by the following two switched-capacitor circuits. A switched-capacitor circuit operates in two clock phases. The two clock phases are complimentary. During 1 phase, all 1 switches are on, while all 2 switches are off. During 2 phase, all 2 switches are on, while all 1 switches are off.

Assumption: 1) linear setting less than 0.1% error (7) completes in a quarter of the clock cycle (T/4); 2) Miller cap Cc=1pF; 3) overdrive voltage Vod=0.2V; 4) all the cap C in the figure above are 1pF.
b) If the static sampling error is less than 0.1%, what should be the OPAMP gain?
c) If OPAMPs have offset, how will offset affects both circuits?
d) Please list the advantages and disadvantages of both circuits.
Solution
a)
For both circuits,

7 T 28 f

7.. .. f ..445.63 MHz (1)
2.fBW 4 BW 2.

For circuit I, the feedback coefficient .I . 1, while .II . 0.5 for circuit II. Therefore,
. f
GBW . BW . f . 445.63MHz
.I BW
.
.I

. (2) . fBW
GBW .. 2f . 891.26 MHz
II BW
..
.II

We know that for two-stage OPAMP,
2I gm Vod

GBW .. (3)
2.Cc 2.Cc
Therefore,
2I

SR ..2.GBWV od (4)Cc .SRI . 560V / .s
. (5)
.SRII . 1.12 kV / .s
b) For circuit I,
A

Acl_I . 1.I A (6) I
For circuit II,
1 AA

A . II . II (7)
cl_II
21 . 0.5 A 2 .A
II II
For both circuits,
.1. A . 0.1%
.cl_I

. (8)
1. A. 0.1%
.cl_II
.
Therefore,
.A . 999 . 60 dB

. I (9)
.AII . 1998 . 66dB
c)

For I, offset will be directly added to the sampled data.
For II, during sample phase 1, the offset will be stored. In hold phase 2, the offset will be canceled from the sampled data.
d)

Circuit II can remove the OPAMP offset. But it requires larger gain and larger GBW. For circuit II, the output loading is C||C, which is much larger than that in circuit I, C||Cgs. This can make the non-dominant pole closer to GBW, leading to small phase margin, even causing instability. Or equivalently, in order to maintain the phase margin, the current for the second stage will increase.
2. (25pts) Fully-differential OPAMPs can be used to implement filters as shown on the left. The schematic of the OPAMP is shown on the right. Please derive the output voltage
dvnof
2 ..
noise density of the filter.
df
Assumption: 1) only thermal noise needs to be considered; 2) only consider dominant noise terms; 3) all transistors have the same gm and rds.